The present invention relates generally to system interconnects and more particularly to a data path architecture and arbitration scheme for providing access to a shared system resource.
Most data processing systems include a system interconnect that enables the exchange of data between system components. Typically, at least one of the system components acts as a resource that is shared by other system components, and the system interconnect provides access to the shared resource. For example, the system memory of a personal computer is typically used by most of the components of the personal computer system, and the data bus of the personal computer system provides access to the system memory.
The manner in which the system interconnect and its associated arbitration scheme are defined determines the minimum xe2x80x9caccess latencyxe2x80x9d to shared resources of the data processing system, wherein the minimum access latency is the minimum amount of delay between the time when a system component requests access to a shared resource and the time when the system component gains access to that resource. For synchronous system interconnects, access latency is typically expressed in xe2x80x9cclock cycles.xe2x80x9d
Typically, if a first system component is performing a multiple clock cycle access to a shared resource, a second system component will be prevented from accessing the shared resource until the first system component has completed its access. Thus, the second system component remains idle while awaiting access, and the effective access latency for the second component is several clock cycles greater than the minimum access latency. The effective access latency becomes a critical parameter for maximizing the efficiency of data processing systems that include high speed system components because such system components may become idle while awaiting access to the shared resource, and the processing capabilities of such system components may be underutilized. Therefore, it is desirable to provide a system interconnect and associated arbitration scheme that minimize the effective access latency to shared resources.
The system interconnect architecture and associated arbitration scheme described below provide for the interleaving of multiple accesses to a shared system resource by multiple system components on a data block by data block basis. According to one embodiment, an access request is granted xe2x80x9cimmediatelyxe2x80x9d upon receipt such that the effective access latency between an access request and the transfer of a first data block (e.g. a byte, a word, a long word, or a double long word as determined by the width or throughput of the data path) for the access is the minimum access latency to the shared system resource. If a second access request is received while a first access is being performed, the second access request is granted immediately, and the first and second accesses are thereafter interleaved such that data blocks of the accesses are alternately transferred by the system interconnect.
According to one embodiment, the system interconnect architecture and associated arbitration scheme are implemented in a data processing system that comprises:
a first system component;
a second system component;
a shared system resource; and
a system interconnect that interleaves a first multi-block access of the shared system resource by the first system component and a second multi-block access of the shared system resource by the second system component such that data blocks of the first and second multi-block accesses are alternately transferred by the system interconnect.
The number of system components for which minimum access latency for the first data block may be guaranteed is determined by the number of accesses that the system interconnect is able to interleave. For the described embodiments, xe2x80x9ctwo accessxe2x80x9d interleaving is provided such that the minimum access latency to starting a data transfer is guaranteed for only two system components. As will be described, the system interconnect architecture may be readily adapted to provide xe2x80x9cn accessxe2x80x9d interleaving wherein n system components are guaranteed minimum access latency for at least the first data block to be transferred.
Other features and advantages of the present invention will be apparent from the accompanying drawings and from the detailed description which follows below.